CXMT fifth-generation DRAM has entered mass production, giving China’s leading memory-chip manufacturer a denser process for smartphones and portable electronics. The company says its new platform reduces key memory-cell feature spacing to 11.95 nanometres while lowering power use and manufacturing cost.

 

ChangXin Memory Technologies announced the platform at the 2026 World Manufacturing Convention in Hefei on September 20. It also unveiled two 24-gigabit LPDDR5X products that hold 50% more data than the company’s previous equivalent chips.

 

CXMT disclosed three production milestones:

  • 11.95-nanometre spacing for key data-storage features
  • Two 24-gigabit LPDDR5X chips already in mass production
  • At least 50% more gross dies per wafer than its prior platform

 

Background Reading

 

CXMT Fifth-Generation DRAM Uses Quadruple Patterning

The new platform relies on quadruple patterning, a manufacturing technique that repeats lithography-related steps to create finer circuit features than a single exposure can produce. CXMT says the process packs the tiny structures that store data closer together, increasing memory density and the number of chips that can fit on a wafer.

 

CXMT reported feature spacing of 11.95 nanometres in the part of the chip that stores data. Vice president Luo Xiaodong described the company’s process capability as comparable with the most advanced nodes currently in mass production, although independent manufacturing data has not yet validated that claim.

 

The company said it developed the platform through computer simulations and joint work with Chinese chip-equipment suppliers on critical production steps. That collaboration is strategically important because advanced semiconductor manufacturing depends on a complex chain of lithography, deposition, etching, inspection and process-control tools.

 

Quadruple patterning can extend established equipment to finer geometries, but it also adds process steps and manufacturing complexity. The commercial test will be whether CXMT can sustain high yields, consistent performance and competitive costs as production volume increases.

 

Two 24-Gigabit LPDDR5X Chips Enter Production

CXMT introduced two 24-gigabit LPDDR5X products built on the fifth-generation platform. LPDDR5X is a low-power form of dynamic random-access memory used primarily in smartphones and other portable electronics, where energy efficiency directly affects battery life and thermal limits.

 

Each new chip stores 50% more data than CXMT’s previous equivalent product. The company is offering two package formats to support different mobile-device designs, giving manufacturers another potential source for higher-density memory.

 

The announcement concerns LPDDR5X rather than the high-bandwidth memory used beside many AI accelerators. Its immediate market impact is therefore more direct for phones, tablets and portable devices than for data-centre training systems.

 

Even so, improved DRAM manufacturing has broader strategic value. A denser, more efficient process can support future product lines, strengthen domestic engineering expertise and free manufacturers to apply lessons from mobile memory to other segments.

 

Gross Dies Per Wafer Rise by at Least 50%

CXMT says the fifth-generation platform produces at least 50% more gross dies per wafer than its fourth-generation process when measured against an 8-gigabit-chip baseline. More dies on the same silicon wafer can improve factory economics because fixed processing costs are distributed across a larger potential output.

 

The gross-die figure is not the same as production yield. It counts the potential number of chips patterned on a wafer before defective units are removed, so final cost and available supply will still depend on how many dies pass testing.

 

That distinction matters when assessing CXMT’s claim of lower production costs. Denser designs can deliver major efficiency gains, but additional patterning steps may raise complexity and defect risk. Sustained yields across large production runs will determine how much of the theoretical wafer advantage reaches customers.

 

The two LPDDR5X products are already in mass production, according to the company. That moves the announcement beyond a laboratory demonstration, though customer adoption, shipment volumes and pricing have not yet been disclosed.

 

CXMT Challenges a Market Led by Three Global Suppliers

The global DRAM market is dominated by Samsung Electronics, SK Hynix and Micron Technology. CXMT remains smaller, but its new platform could provide device makers with another supplier and give China a stronger domestic option for an essential semiconductor category.

 

The timing also reflects Beijing’s effort to reduce dependence on foreign chip technology. United States export controls introduced since 2022 have restricted China’s access to certain advanced semiconductor equipment and software, increasing pressure on Chinese manufacturers to develop local tools and processes.

 

CXMT listed on Shanghai’s STAR Market in 2026 and has continued expanding its manufacturing ambitions. The fifth-generation platform shows technical progress, but competition with established suppliers will be decided by production yield, reliability, customer qualification and the ability to scale without eroding cost advantages.

 

For the memory industry, the most consequential detail is that the company has moved two denser products into commercial production. If CXMT delivers the claimed wafer economics at acceptable yields, the platform could widen supply options and intensify competition in mobile DRAM.